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Engineering Change Notice (ECN) — Cassini Test Instrument Module (TIM)

ECN: RBEH-DRTVM4
Title:
[Short, action-oriented summary of the change]
Originator:
[Name, Title, Dept]
Date Submitted:
[YYYY-MM-DD]
Change Type:
[Minor / Major / Sustaining / Corrective / Obsolescence / Cost-Down]
Urgency:
[Normal / Expedite / Stop-Ship]
Confidentiality:
[Internal / Supplier-Shared]




1) Affected Configuration Items
    • Module Name: Cassini TIM – [Instrument family / function]
    • TIM Part Number (PN): [PN]
    • TIM Assembly PN / Rev: [PN-ASM] / [Rev]
    • Serial Numbers / Lots: [SNs / Lot IDs]
    • Firmware / FPGA / Bitstream:
        • FW: [Name] v[old] → v[new]
        • FPGA/Bitstream: [ID] v[old] → v[new]
        • Bootloader: [if applicable]
    • Calibration Data: [Cal profile v[old] → v[new] / unchanged]
    • Test Limits / Test Plan: [Doc-ID] v[old] → v[new]
    • Mechanical/PCB/Connector: [PCB PN/Rev, Mech PN/Rev, Connector PN]
    • Cables/Harnesses/Fixtures: [IDs and Revs]
    • BOM Line Items Impacted:
        • [RefDes / Component PN / Old Rev → New Rev] (LC/NC?)
    • Software/Driver/SCPI Interface: [Driver pkg / API / SCPI command set changes]


2) Reason / Problem Statement
    • Issue / Driver: [Defect, performance drift, reliability, obsolescence, supply, safety, cost]
    • Evidence / Data: [FA results, yield data, field returns, logs]
    • Customer / Compliance Impact: [If any]


3) Change Description (What is changing?)
    • Functional change: [What functionality or performance is added/removed/modified]
    • Design change: [Schematics, layout, logic, HDL, timing, algorithm]
    • Parameters / Limits: [Old spec → New spec with units and tolerances]
    • Interfaces:
        • Electrical: [Voltage/current ranges, impedance, timing]
        • Mechanical: [Envelope, mounting, weight, connector keying]
        • Software/API/SCPI: [New/removed commands, response formats, error codes]
    • Documentation: [Docs to be revised and version increments]
    • Backwards compatibility: [Yes/No — explain]


4) Impact Assessment

Form / Fit / Function (FFF):

    • Form: [Enclosure, PCB outline, labels, ROHS markings]
    • Fit: [Mounting holes, connector mating, harness length]
    • Function: [Accuracy, resolution, bandwidth, noise, linearity, timing]
Performance / Metrology:
    • Accuracy/Uncertainty: [Before → After, include guard-bands]
    • Repeatability/Reproducibility: [Before → After]
    • Latency/Throughput: [Before → After]
Calibration:
    • Recalibration required? [Yes/No]
    • Cal constants / method changes: [Describe]
    • Calibration fixtures / standards impacted: [List]
Verification & Validation:
    • Regression tests impacted: [List test IDs]
    • New tests required: [List, with acceptance criteria]
    • Environmental/EMC/ESD/HiPot: [Required? Results if pre-run]
Manufacturing / Test:
    • Process/fixture changes: [Work instructions, ICT/JTAG, ATE sequences]
    • Cycle time / throughput impact: [Δ minutes/part]
    • Yields / scrap risk: [Estimate]
    • Special tooling: [If any]
Field / Service:
    • Field-upgradeable? [Yes/No — steps or N/A]
    • Swap criteria: [RMA thresholds / SN range]
    • Downtime risk / mitigation: [Plan]
Supply Chain / Cost:
    • AVL / AML updates: [Approved vendors, alternates]
    • Availability / lead time: [Δ weeks]
    • Cost impact (Unit / NRE): [+$/-$]
    • End-of-Life / Last-Time-Buy: [If relevant]
Quality / Reliability / Safety:
    • FMEA delta: [New failure modes, severity, occurrence, detection]
    • HALT/HASS / Life test: [Needed? Status]
    • Regulatory: [RoHS/REACH/CE/UKCA/UL/CSA/CB — impacts/unchanged]
    • ESD / Latch-up / Over-voltage: [Mitigations]
Cybersecurity / Data Integrity (if connected):
    • Interfaces: [USB, LAN, PXI, proprietary]
    • Auth/Update signing: [Bootloader/firmware signing, rollback protection]
    • Diagnostic/Debug ports: [Lockdown status]


5) Risks & Mitigations
Risk ID
Description
Likelihood
Impact
Mitigation / Contingency
Owner
Due
R1
R2



6) Implementation Plan

Effective Date / SN Break: [Date] / [First good SN: …] **Phased Rollout:**[Pilot → Limited → Full] **Manufacturing cut-in:**[WO/PO rules, rework vs scrap] **Field upgrade plan:**[Kits, instructions, time, tools] **Dependencies:**[Other ECNs/PCNs, material arrival, approvals] **Training:**[Ops, Quality, Service, Applications] **Communications:**[Internal bulletin, Supplier PCN, Customer notice]`




7) Verification & Acceptance Criteria
    • Test matrix: [List required tests; link test script IDs]
    • Acceptance thresholds: [Numeric criteria with units]
    • Sample size & confidence: [e.g., n=30 @ C=0 AQL 0.65]
    • Data storage / traceability: [MES/PLM record IDs]
    • Sign-off gates: [Pilot pass, MRB exit, PQC sign-off]


8) Documentation & Systems to Update
    • Schematics / PCB layout [Doc IDs → new rev]
    • BOM & AML/AVL [BOM-### vX → vY]
    • Mechanical drawings / STEP [IDs]
    • Firmware/FPGA repos & release notes [Tags, hashes]
    • Calibration procedures & certificates [Doc IDs]
    • Manufacturing work instructions (WI/SOP) [IDs]
    • Test procedures & limits [ATE scripts, limits files]
    • User manual / datasheet / label artwork [IDs]
    • PLM / ERP [Item/Rev status changes]
    • Service docs / field bulletins [IDs]


9) Disposition of Existing Stock / WIP / Returns
    • Raw/Kit/WIP: [Use as-is / Rework / Scrap]
    • Finished Goods: [Rework criteria, quarantine rules]
    • RMA / Field returns: [Segregation and rework path]


10) Approvals
Role
Name
Signature / Date
Design Owner
Systems / Metrology
Manufacturing Engineering
Test Engineering
Quality / Reliability
Supply Chain / Sourcing
Compliance / Safety
Service / Field
Configuration Management (CM)
MRB Chair (if applicable)



Attachments (check all that apply)
    • Updated schematics / layout diffs
    • BOM delta report
    • Firmware/FPGA release notes & binaries
    • Calibration data / MSA report
    • Test limit files & regression results
    • FMEA update
    • Costed BOM and AVL/AML updates
    • Risk register & mitigation plan
    • Customer notice / Supplier PCN (if external)


Quick-Reference (One-Page Summary)

ECN No. / Title:
Scope:
[HW / FW / FPGA / Cal / Test Limits / Docs]
Why:

What changes:

Impacts:

    • FFF: [/ + brief]
    • Performance/Accuracy: [Δ]
    • Calibration: [Req’d?]
    • Manufacturing/Test: [Fixture/Script Δ]
    • Field/Service: [Upgrade path]
    • Cost/Lead time: [Δ]
      Cut-in:
      [Date / SN break]
      Acceptance:
      [Key tests + thresholds]
      Owners:
      [Design / Test / MFG / Quality]
      Approvals:
      [Blocks remaining]


Notes & Tips for Cassini TIMs
    • SCPI/API stability: Document any command additions, removals, or response format changes. Provide a compatibility shim if breaking changes are unavoidable.
    • Calibration: If algorithms or measurement chains change (e.g., ADC path, filtering, linearization), recompute uncertainty and update cal procedures and certificates.
    • FPGA/HDL: Include bitstream ID, synth tool version, and timing closure artifacts. Attach pre/post loopback and BIST results.
    • Test Limits: If test plan or ATE scripts change, attach diffs and limit file versions; rerun regression across historical golden units.
    • Labeling/Traceability: Ensure Rev, FW, and Cal versions are visible in self-test/*IDN? or equivalent identification commands for field traceability.

Published: 03/03/2026 03:32:52 PM Modified: 03/03/2026 05:15:49 PM
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